These demos present an in-depth view of various programmable
design products relative to chip vendors. Scroll down to view all demos or select a vendor name from either
menu.
Quartus II Software Overview
The Quartus® II software is the only design environment available that supports FPGA, CPLD, and structured ASIC
HardCopy™ device designs. The following demonstration will show how easy it is to get started using the Quartus
II software as well as highlight what’s new in the latest
version of the software.
Basic FPGA/CPLD Design
The Altera® Quartus® II design software provides a complete, multiplatform design environment that easily adapts to your specific design needs.
It is a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes solutions for all phases of FPGA and CPLD design from design entry and
HDL synthesis to verification and programming. These demonstrations show the basic design procedures in the Quartus? II software.
Design Flows
The Quartus® II software supports many design flows to help you design for systems-on-a-programmable-chip and reach timing closure faster.
Design Optimization & Implementation
The Quartus® II software optimizes design performance
to reach timing closure faster. These demonstrations
provide an overview of available Quartus II features
that will help optimize design performance.
Shortening Design Cycles
The Quartus® II software provides many features to help
reach timing closure faster. These demonstrations give
an overview of some of the features available in the
Quartus II software to shorten overall design cycles.
Verification
The Quartus II software provides many features to help verify the functionality of any design and debug any
issues. These demonstrations provide an overview of some of the verification features available in the Quartus
II software.
Nios II Embedded Processor
Altera introduces the Nios® II family of embedded processors, extending the performance and lowering the cost of the
world’s most popular soft embedded processor. Designed for use in Altera’s Stratix® II, Stratix, Cyclone™,
and HardCopy® device families, Nios II designers can achieve performance over 200 DMIPS and spend as little
as 35 cents on logic. With three processors and over 60 intellectual property (IP) cores from which to choose,
Nios II systems provide the ultimate in versatility, letting designers create the perfect fit for their embedded
system needs.
