These demos present an in-depth view of various back end design products relative to extraction. Scroll down
to view all demos or select a vendor name from either menu.
Speed Signal Integrity Closure with CeltIC™ Crosstalk Analyzer and Fire & Ice® QXC Extractor
See how CeltIC and Fire & Ice QXC are used for extraction, signal integrity analysis, and repair within the SoC
Encounter flow. This highly accurate combination filters out most false signal integrity violations, thus enabling
rapid signal integrity closure with sign-off quality results.
Solving New Challenges in Nanometer Design with Assura™ Physical Verification
In nanometer design, physical verification including
layout parasitic extraction is a must to achieve manufacturing
sign-off. This demonstration features the use of Assura
RCX, the industry’s standard for 3D device-level parasitics
extraction, to accurately extract and optimize the on-chip
parasitics of a VCO block generating an Extracted View
with parasitics for subsequent simulation of a digital/mixed-sign
design. An overview of the Assura DRC, LVS for nanometer
designs will also be presented. (This demo features a previous release of Assura physical verification).
COLUMBUS-AMS™ - To Explore Superior
Technology For Resistance, Capacitance, Inductance
Leveraging production-proven Columbus RLC extraction technology for GDSII flows, it features new Smart Probing technology and Calibre integration in the Cadence Analog Design Environment.
