Cooley's Hot Videos

DVCon 2008 - Troublemaker's Panel

This year's Troublemaker's Panel discussed Mike Santarini, DataQuest, VC's, Nvidea, real estate agents, power, US engineering grads, 9/11, India, H1-B visas, outsourcing, Cadence, Freescale, NXP, bookings bubbles, Verisity Specman, Verilog, P&R, Magma, Sierra, data management, Synchronicity, design teams too large, exit strategies, intelligent testbenches, Wally Rhines, ESL, SystemC, ANSI C, System Verilog, Matlab, parallel computing, Rajeev Madhavan, EDAC, Talus, Magma, Synopsys lawsuit, Atoptech, Broadcom, Sierra, Avanti, Mojove, Gerry Hsu, Synopsys Orion, Milkyway, OA, Virtuoso, Pcells, PDKs, QuickCap, Silicon Canvas, Dracula, VHDL, FPGAs, Mach TA, Adit, AVM, OVM, all-you-can-eat-FAM deals, cost of design, start-ups, Cadence, Mentor, Sierra, Atoptech, ICC, Magma, DFM, ClearShape, Invarium, AutoESL, CatapultC, SW discounting, India, Fast SPICE, UPF vs. CPF, Ciranova, Pcells, and US kids studying engineering.

Related Demos

Liberate™ and Variety™: Ultra fast IP Characterization Solutions from Altos Design Automation

This demo provides an in depth look at Liberate™ and Variety™, a new generation of IP characterization products from Altos Design Automation Inc. Utilizing Altos' novel "inside view" approach, the demo shows how characterization can be sped up significantly yet still yield the same accuracy with better model quality that existing approaches. The demo also highlights the challenges of modeling process variation and how Variety enables the creation of statistical timing libraries in order to reduce design guard bands thereby enabling faster timing closure and lower power consumption.

Blaze Torch Technology Demonstration

The Blaze "Torch" lithography-aware analysis and optimization technology enables chip designers to model and compensate for litho-induced process variations when working with silicon technologies of 65nm and below. Blaze Torch technology employs the production-OPC "Halo" lithography simulation engine to model the effects of process variations on power and performance. It uses built-in timing and power optimization algorithms to automatically compensate for these variations. It also identifies litho hot-spots that could lead to physical defects, and produces a repair guidance file for automatic defect repair using third-party physical design tools.

Booting and Debugging Linux in Emulation with ZeBu

Can you cycle-accurately boot a complete operating system and debug concurrently at the hardware and software level? With ZeBu, a hardware-assisted verification platform, you can. This demo walks you through a few HW/SW bugs encountered during the boot of a Linux kernel and web browser application software, and shows how bugs in hardware and software can be isolated, reproduced and fixed faster than ever before.

Improving Test Quality at 65 nm and Below with Talus ATPG

The increased complexity and smaller feature sizes of today's chip designs make it more complicated to test manufactured ICs. Traditional test approaches lack the performance, accuracy and capacity to deliver the required level of test quality and turnaround time for nanometer ICs. View this demo to learn how Magma's advanced Talus® ATPG and Talus ATPGX software allows designers to improve test quality and turnaround time.